Many applications in modern electronics require that discrete-time signals, generated using computers and digital signal processors, be converted to linear (analog) signals, e.g., for transmission as electromagnetic signals. Typically, this transformation is made using a conventional digital-to-analog converter (DAC). However, the present inventor has discovered that each of the presently existing converters exhibits shortcomings that limit overall performance at very high sampling rates.
Due to parallel processing and other innovations, the digital information processing bandwidth of computers and signal processors has advanced beyond the capabilities of state-of-the art DACs. Therefore, converters with higher instantaneous bandwidth are desired. Existing solutions are limited by instantaneous bandwidth (sampling rate), effective conversion resolution (accuracy), or both.
The resolution of a DAC is a measure of the precision with which a quantized signal can be transformed into a continuous-time continuously variable signal, and typically is specified as a ratio of the total signal power to the total noise plus distortion power at the DAC output. This signal-to-noise-and-distortion ratio (SNDR) of a DAC is commonly expressed on a logarithmic scale in units of decibels (dB). When a discrete-time discretely variable (digital) signal is converted into a continuous-time continuously variable (analog) signal, the quality of the analog signal is corrupted by various limitations and errors introduced during the conversion process. Examples include: 1) the finite granularity of the DAC output levels, which produces quantization noise; 2) the imprecise (e.g., nonlinear) mapping of digital inputs to corresponding discrete output voltage or current levels, which introduces distortion in the form of rounding inaccuracies (rounding errors); 3) the imperfect timing between transitions in output voltages or currents relative to transitions in digital inputs, which causes noise in the form of sampling jitter; and 4) the thermal noise associated with active devices (e.g., switches and amplifiers) which couples onto the DAC output. High-resolution converters transform discrete signals into continuously variable signals using a rounding operation with fine granularity, and a more linear mapping of digital inputs to output voltage and/or current. Instantaneous conversion bandwidth is limited by the Nyquist criterion to a theoretical maximum of one-half the converter sampling rate (the Nyquist limit), such that aliasing occurs when the converted signal contains frequency components which exceed the Nyquist limit. High-resolution conversion (of ≧10 bits) conventionally has been limited to instantaneous bandwidths of about a few gigahertz (GHz) or less.
Converters that transform digital signals into analog signals with fine granularity (i.e., transform a digital signal using many discrete output levels) and a sampling rate fS that is equal to, or just greater than, twice the maximum frequency fMAX spanned by the digital signal, are conventionally known as Nyquist-rate converters, or Nyquist converters. Conventional Nyquist-rate converters include those implemented using resistor ladder networks (e.g., R-2R ladders), or those employing switched current/voltage sources with unitary (i.e., equal) weighting or binary weighting. A conventional R-2R ladder DAC, such as that shown in FIG. 1A, generates a variable output voltage at levels equal to the binary-weighted sum of multiple, two-level (i.e., digital) inputs. The voltage summation operation is performed using a network of resistors, having appropriately weighted (i.e., binary-weighted) resistance. The voltage at the output of the resistor network sometimes is buffered, and/or sometimes is smoothed using an analog lowpass filter, to produce a continuously variable signal. An alternative DAC structure is illustrated in FIG. 1B, which instead of a resistor ladder network, uses a switched bank of current sources to generate a variable output current equal to the binary-weighted sum of digital inputs. As shown in FIG. 1B, the output current sometimes is converted to a proportional output voltage using a transimpedance amplifier (i.e., a current-to-voltage converter).
Conventional Nyquist-rate converters potentially can achieve very high instantaneous bandwidths, but as discussed in greater detail below, the present inventor has discovered that component mismatches in the resistor ladder network, or in the switched current sources, can introduce rounding errors that significantly limit attainable resolution. In addition, the resolution of conventional Nyquist-rate converters is limited by other practical implementation impairments such as sampling jitter and thermal noise. Although in theory, Nyquist-rate converters potentially could realize high resolution at instantaneous bandwidths greater than 10 GHz, this potential has been unrealized in conventional Nyquist-rate converters due to the foregoing problems.
A conventional approach that attempts to reduce quantization noise and errors uses an oversampling technique. Conventional Nyquist-rate converters transform digital input samples into variable-level output samples (i.e., as a voltage or a current), such that a single input sample is represented by a single output sample, and the value of each output sample is proportional to the digital input. In contrast, conventional oversampling converters transform digital input samples into outputs which are pseudorandom sequences of two-level samples (i.e., output samples having a single positive level or a single negative level), such that: 1) a single input sample is represented by multiple output samples; and 2) the average of these multiple output samples is proportional to the digital input. Therefore, oversampling converters generate coarse (e.g., two-level) analog voltages or currents at a sampling rate (i.e., fS) that is much higher than twice the occupied bandwidth fB of the input signal (i.e., fS>>fB), where: 1) fB is equal to the Nyquist frequency fMAX for lowpass (baseband) input signals; and 2)
  N  =            1      2        ·                  f        S            /              f        B            is conventionally referred to as the oversampling ratio of the converter. A continuously variable output that is proportional to the digital inputs is produced from the pseudorandom sequences of two-level outputs, using a filtering operation that effectively averages the output samples. Although this averaging process reduces the instantaneous bandwidth of the oversampling converter (i.e., the maximum frequency that can be converted without exceeding the Nyquist limit), it has the benefit of improving the converter resolution by attenuating quantization noise (i.e., the noise introduced by using only two levels to represent a continuously variable signal) and errors resulting from component mismatches, sampling jitter, and thermal noise. The extent of this benefit is directly related to the output sampling rate fS (i.e., the benefit increases as the sampling rate increases), and is conventionally enhanced using oversampling in conjunction with an operation referred to as noise-shaped quantization, that ideally attenuates conversion noise and errors in the signal bandwidth without also attenuating the signal itself. Through this noise-shaped quantization operation and subsequent filtering (i.e., output averaging), oversampling converters transform a high-rate intermediate signal having low resolution, into a relatively low bandwidth output signal having improved resolution.
FIGS. 2A&B illustrate block diagrams of conventional, lowpass oversampling converters 5A and 5B, respectively. A conventional lowpass, oversampling converter typically uses delta-sigma (ΔΣ) modulation (e.g., modulators 7A&B) to coarsely quantize a digital input signal, in a manner where the noise introduced by coarse quantization is shaped with a high-pass response. The input (e.g., signal 3) to each of ΔΣ modulators 7A&B is a high-rate signal, with a sampling rate fS=fCLK>>2·fMAX (i.e., the sampling rate fS is equal to the modulator clocking rate fCLK, and is greater than twice the maximum frequency fMAX spanned by both digital input 2 and modulator input 3). More specifically, modulator input 3 is a high-rate (oversampled) representation of input signal 2, such that modulator input 3 and digital input 2 are, respectively, high-rate and Nyquist-rate representations of the same underlying continuous-time signal. Conventionally, modulator input 3 is generated from digital input 2 using a sample-rate conversion operation (e.g., rate converter 6) which comprises: 1) upsampling by the converter oversampling ratio N (e.g., via zero-insertion within upsampler 6A); and 2) lowpass filtering (e.g., within filter 6B) to remove the unwanted signal images produced by zero-insertion. As the name implies, delta-sigma modulators 7A&B shape the noise introduced by two-level quantizer 10 via difference operation 8 (i.e., delta) and integration operation 13 (i.e., sigma), where
      I    ⁡          (      z      )        =      1          1      -              z                  -          1                    is the response of integrator operation 13 and z−1 represents a unit delay equal to 1/fCLK (i.e., z−1 represents a delay corresponding to one cycle of the modulator clocking rate fCLK). Converter 5A, shown in FIG. 2A, uses what is conventionally referred to as an interpolative ΔΣ modulator circuit (e.g., modulator 7A). Alternatively, circuit 5B shown in FIG. 2B, utilizes a lowpass ΔΣ modulator (e.g., modulator 7B) with a conventional error-feedback structure. See D. Anastassiou, “Error Diffusion Coding in A/D Conversion,” IEEE Transactions on Circuits and Systems, Vol. 36, 1989.
Generally speaking, the delta-sigma modulator processes the signal with one transfer function (i.e., the signal transfer function or STF) and the quantization noise with a different transfer function (i.e., the noise transfer function or NTF). Conventional transfer functions (i.e., after accounting for the implicit delay of the clocking operation on two-level quantizer 10) are of the form STF(z)=z−k and NTF(z)=(1−z−1)P, where k is an integer and P is called the order of the modulator (or order of the noise-shaped response). Converter circuits 5A&B employ first-order ΔΣ modulation (i.e., P=1) that produces STF frequency response 30 and NTF frequency response 32 that are shown in FIG. 2C. For both circuits 5A&B, the output sampling rate fS, and therefore the converter oversampling ratio N, is determined by the clock frequency fCLK of delta-sigma modulator 7A&B (i.e., shown as the input clock to the two-level quantizer 10 in FIGS. 2A&B), such that fS=fCLK.
For a given converter resolution, the bandwidth of a conventional oversampling converter typically is increased by increasing the clocking frequency fCLK of the ΔΣ modulator (i.e., increasing the sampling rate fS), thereby making the oversampling ratio N higher. Similarly, for a given bandwidth, a higher oversampling ratio N results in improved converter resolution. Generally speaking, the present inventor has determined that the resolution B of a conventional oversampling converter is given by
      B    =                  Δ        ⁢                                  ⁢        Q            -                        1          2                ·                              log            2                    ⁡                      (                                          ∫                0                                                      f                    S                                    /                  2                                            ⁢                                                                    1                    12                                    ·                                                                                                                                    NTF                          ⁡                                                      (                                                                                          ⅇ                                                                  2                                  ⁢                                  π                                  ⁢                                                                                                                                          ⁢                                  j                                  ⁢                                                                                                                                          ⁢                                  fT                                                                                            ,                              P                                                        )                                                                          ·                                                  F                          ⁡                                                      (                                                          ⅇ                                                              2                                ⁢                                π                                ⁢                                                                                                                                  ⁢                                j                                ⁢                                                                                                                                  ⁢                                fT                                                                                      )                                                                                                                                      2                                                  ⁢                                  ⅆ                  f                                                      )                                ,where ΔQ is the number of bits at the output of quantization circuit 10 (i.e., level of coarse quantization which typically is equal to one bit) and F(e2πjfT) is the frequency response of output filter 12. Increasing the clock frequency fCLK of the ΔΣ modulator requires circuitry with higher speed capability, and generally, higher power dissipation. Alternatively, higher bandwidth and/or improved resolution are realized by increasing the order P of the ΔΣ modulator. Compared to converter circuits 5A&B, lowpass oversampling converter 5C, illustrated in FIG. 2D, realizes higher bandwidth (or improved resolution) using interpolative ΔΣ modulator circuit 7C, which incorporates two integration operations (i.e., circuits 13A&B) to produce a noise-shaped response that is second-order (i.e., P=2). Increasing the modulator order P, however, causes undesirable reductions in the stability of the modulator. The present inventor has discovered, for example, that a ΔΣ modulator of order four or higher is unstable with two-level (i.e., ΔQ=1 bit) quantization. The present inventor also has discovered that the multi-level quantization circuits needed to stabilize high-order modulators introduce rounding errors that are not subjected to the noise-shaped response of the ΔΣ modulator. As a result of constraints on the operating speed (i.e., clocking rate) of conventional ΔΣ modulator circuits and on the rounding accuracy of multi-level quantization circuits, increasing the clocking frequency and/or the order of the ΔΣ modulator has limited utility in improving the bandwidth and/or resolution of conventional oversampling converters.
The delta-sigma converters 5A-C illustrated in FIGS. 2A,B&D are conventionally known as lowpass, delta-sigma converters. A variation on the conventional lowpass converter employs bandpass delta-sigma modulation to allow conversion of narrowband signals that are centered at frequencies other than zero. Exemplary bandpass oversampling converter 40A, illustrated in FIG. 3A, includes bandpass delta-sigma modulator 42 that shapes noise from two-level quantizer 10 by performing difference operation 8 (i.e., delta) and integration operation 14 (i.e., sigma), where
      H    ⁡          (      z      )        =            z              -        1                    1      +              z                  -          2                    is the response of integration operation 14 and z−1represents a unit delay equal to 1/fCLK. After accounting for the implicit delay of the clocking operation on two-level quantizer 10, conventional bandpass ΔΣ modulator 42 has a STF(z)=z−1 and a second-order NTF(z)=1−z−2. Like converter circuits 5A&C, bandpass oversampling converter circuit 40A is an interpolative structure that produces signal response 70, shown in FIG. 3B, that is different from its quantization noise response 71. As shown in FIG. 3B, the bandpass modulator of FIG. 3A has a NTF with a minimum magnitude (i.e., spectral null 72) at a frequency of
                    1        4            ·              f        S              =                  1        4            ·              f        CLK              ,which is at the center of the converter Nyquist bandwidth. Producing a NTF with a spectral null at a frequency other than zero hertz requires a real ΔΣ modulator with, at minimum, a second-order response (i.e., the delay operator z is raised to a power of −2), and in general, the NTF of a bandpass ΔΣ modulator is of the form (1+ρ·z−1+z−2)P, where −2≦ρ≦+2. Although signal response 70 of circuit 40A is all-pass, the present inventor has discovered that, in general, the STF of bandpass oversampling converters is not all-pass when interpolative modulator structures are employed. Conversely, the present inventor has discovered that bandpass oversampling converters which utilize the alternative error-feedback structure of FIG. 2B, have an STF which is uniformly all-pass. After two-level quantization (e.g., within quantizer 10), the bandpass filtering of quantization noise takes place (e.g., within filter 43) in a manner similar to that performed in the standard conventional lowpass oversampling converter (e.g., either of converters 5A&B). In FIG. 3A, it is assumed that the sampling rate of the digital input is equal to the clocking rate fCLK of the overall converter (i.e., the clocking rate of the modulator), and therefore, a sample-rate conversion (upsampling) operation is not included. In cases where the sampling rate of the digital input is lower than the clocking rate fCLK of the overall converter, however, a sample-rate conversion (upsampling) operation would be included.
Although oversampling with noise-shaped quantization can reduce quantization noise and other conversion errors, the output filtering (i.e., smoothing) operations generally limit the utility of oversampling converters to applications requiring only low instantaneous bandwidth (e.g., input signals with low frequency content). Conventional schemes for overcoming the bandwidth and resolution limitations of data converters generally have been devised with a focus on the conversion of analog (linear) signals to digital (discrete) signals (i.e., analog-to-digital conversion), rather than on the conversion of digital signals to analog signals (i.e., digital-to-analog conversion), which is the subject of the present invention. The present inventor has discovered that these conventional schemes for improving bandwidth and/or resolution in analog-to-digital conversion suffer from significant disadvantages, particularly in attempts to directly adapt these schemes for use in digital-to-analog conversion applications.
For example, one attempt to overcome the instantaneous bandwidth limitations of high-resolution, analog-to-digital (A/D) converters is conventional hybrid filter bank (HFB) converter 50, illustrated in FIG. 4A. See A. Petraglia and S. K. Mitra, “High Speed A/D Conversion Using QMF Banks,” Proceedings: IEEE Symposium on Circuits and Systems, 1990. A conventional HFB converter consists of multiple narrowband converters that are operated in parallel, such that: 1) a wideband, analog signal is spectrally decomposed into multiple narrowband segments (i.e., sub-bands), using an array of analog bandpass filters (i.e., analysis filters 52A-C) with minimally overlapped frequency responses; 2) each sub-band is downconverted (i.e., within downsamplers 53) and digitized using a low-speed converter (e.g., A/D circuits 54); 3) the digitized outputs of each converter 54 are upconverted (i.e., within upsamplers 56); and 4) the outputs are then combined using an array of digital bandpass filters (i.e., synthesis filters 58A-C) with frequency responses that precisely overlap to create an overall response that is all-pass (i.e., the digital filters have near-perfect signal reconstruction properties). For the conversion of digital signals into analog signals, the present inventor has contemplated a complementary scheme, whereby direct adaptation: 1) analog analysis filters 52A-C at the converter input are moved to the converter output and become signal synthesis filters; 2) analog-to-digital converters 54 are replaced with digital-to-analog converters; and 3) digital synthesis filters 58A-C are moved to the converter input and become signal analysis filters. However, the present inventor has discovered that the performance of this complementary scheme is limited by the intermodulation distortion (i.e., intermodulation or non-ideal cross-products) of the analog mixers needed for the analog upconversion operation. The present inventor also has discovered that at high sampling rates (e.g., greater than several gigahertz), the complexity of multiple digital analysis filters (i.e., one per processing branch) can be prohibitive in many applications, such as those where more than just a few parallel processing branches are needed to realize desired conversion bandwidth and resolution performance.
A second attempt to overcome the instantaneous bandwidth limitations of high-resolution, analog-to-digital (A/D) converters is conventional Multi-Band Delta-Sigma (MBΔΣ) converter 70, shown in FIG. 4B. See Aziz, P., “Multi Band Sigma Delta Analog to Digital Conversion”, IEEE International Conference on Acoustics, Speech, and Signal Processing, 1994. The conventional MBΔΣ approach is similar to the conventional HFB approach except that use of bandpass ΔΣ converters, instead of lowpass A/D converters, eliminates the need for analog analysis filters (e.g., filters 52A-C of circuit 50 in FIG. 4A), downconversion operations (e.g., downsamplers 53 of circuit 50 in FIG. 4A), and upconversion operations (e.g., upsamplers 56 of circuit 50 in FIG. 4A). For converting digital signals to analog signals, the present inventor has contemplated a complementary scheme whereby direct adaptation: 1) analog ΔΣ modulators 72 are replaced with equivalent digital ΔΣ modulators; and 2) digital synthesis filters 73A-C are replaced with equivalent analog synthesis filters. The present inventor, however, has discovered that the sampling rate (i.e., oversampling ratio) of this complementary scheme is limited by the clocking rates (i.e., or switching speeds) of the digital logic needed to implement the digital ΔΣ modulators (i.e., a less significant limitation in analog implementations). Furthermore, the present inventor also has discovered that this complementary scheme is impractical because it requires a bank of analog (continuous-time) filters whose individual responses replicate those of high-order, digital filters with perfect reconstruction properties (i.e., a bank of filters with an overall response that is all-pass). Unlike the HFB approach of FIG. 4A, where imperfections in the analog filter bank are mitigated by increasing the complexity of the associated digital filter bank (see S. R. Velazquez, T. Q. Nguyen, and S. R. Broadstone, “Design of Hybrid Filter Banks for Analog/Digital Conversion,” IEEE Transactions on Signal Processing, 1998), the conventional MBΔΣ approach provides no means of compensating for the amplitude and group delay distortion introduced by analog filter banks with imperfect signal reconstruction properties. Use of direct digital-to-analog filter transformations (i.e., those based on conventional bilinear or impulse-invariant transforms) to design analog filter banks with an all-pass response, generally results in individual analog filters of unmanageable complexity (i.e., filter orders of 30 or more). Approximations to these direct transformations conventionally support only a small number of parallel processing paths (e.g., see A. Fernandez-Vazquez and G. Jovanovic-Dolecek, “Design of Real and Complex Linear-Phase IIR Modified QMF Banks,” IEEE Asia Pacific Conference on Circuits and Systems, 2006), and/or require circuits that are not practical for operation at multi-gigahertz sampling rates, such as switched-capacitor or other impractical circuits (e.g., see P. C. R. Brandao and A. Petraglia, “A Switched-Capacitor Hadamard Filter Bank in 0.35 μm CMOS,” Proceedings: 48th Midwest Symposium on Circuits and Systems, 2005; P. M. Furth and A. G. Andreou, “A Design Framework for Low Power Analog Filter Banks”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1995). As discussed in greater detail below, however, the present inventor has discovered that with relatively minor modifications to standard filter responses (e.g., only center frequency, bandwidth, and/or order), the residual amplitude and group delay distortion introduced by the analog filter bank can be reduced to levels that are acceptable in many applications.
In addition to the conventional frequency-interleaved schemes employed by converters 50 and 70 (i.e., schemes involving spectral decomposition of the converter input signal), another attempt at overcoming the instantaneous bandwidth limitations of high-resolution, analog-to-digital converters involves the use of conventional time-interleaving to increase the bandwidth, or equivalently, the sampling rate of a ΔΣ modulator. Circuits 80A&B, which are illustrated in FIGS. 5A&B, respectively, are conventional time-interleaved ΔΣ modulators that employ a time-interleaving factor of m=2 (i.e., two parallel processing paths). Conventional time-interleaved ΔΣ modulators, such as circuits 80A&B, are interpolative structures wherein the loop filter, or integrator function (i.e., integrator 13 of circuit 80A and integrators 13A&B of circuit 80B), is performed by circuits that operate in parallel. This process of implementing a particular function using parallel processing paths (i.e., parallel circuits) is sometimes referred to in the prior art as polyphase decomposition, or multirate processing. In conventional multirate processing, the output of each parallel processing path is the sub-rate sequence of samples that would be produced by subsampling, at a particular sample-time offset (i.e., at a particular subsampling phase), the sequence of samples generated at full-rate by a complete function (i.e., the output of each parallel path represents a different polyphase component of a complete signal). The ratio of the effective sampling rate (i.e., the full-rate associated with the complete function) to the parallel subsampling rate (i.e., the sub-rate associated with each parallel processing path) conventionally is referred to as the polyphase decomposition factor, and is generally equal to the number of parallel processing paths. More specifically, the operation of a processing function after polyphase decomposition by m is such that: 1) the data samples from the first parallel output correspond to the subsamples taken every mth (full-rate) sample-time period (i.e., subsampling by m), starting with the first sample (i.e., the outputs of the first parallel path are the even subsamples for m=2); and 2) the data samples from the mth parallel output correspond to the subsamples taken every mth (full-rate) sample-time period, starting with the mth sample (i.e., the output of the second parallel path are the odd subsamples for m=2).
In circuits 80A&B of FIGS. 5A&B, the integrator function has been decomposed into two parallel paths (i.e., resulting in a polyphase decomposition factor of m=2), and the delay operator z represents a sub-rate
  (            i      .      e      .        ,                  1        m            ·              f        S              )delay equal to 2/fS, where fS is the sampling rate of the complete converter (i.e., the full-rate before polyphase decomposition). Circuit 80A is a lowpass modulator with a NTF response that is first-order (i.e. , P=1), and circuit 80B is a lowpass modulator with a NTF response that is approximately second-order (i.e., P=2). But rather than decomposing the entire modulator into parallel (polyphase) circuits, in such conventional converters the difference function of the modulator (i.e., subtractors 8A&B of circuit 80A&B) and the quantization function of the modulator (i.e., quantizers 10A&B in circuits 80A&B) are simply replicated m times and distributed across the m parallel processing paths. See R. Khoini-Poorfard, L. B. Lim, and D. A. Johns, “Time-Interleaved Oversampling A/D Converters: Theory and Practice,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1997. As discussed in greater detail below, the present inventor has discovered that simple replication and distribution of the difference and quantization functions (i.e., using time-interleaving through simple replication rather than through polyphase decomposition) causes conventional time-interleaved ΔΣ modulators to exhibit undesirable properties that prevent their use in very high-rate converter applications.
Referring to conventional circuit 80A of FIG. 5A, which utilizes transparent (i.e., unclocked) quantizers with no implicit delay, it can be shown that the quantized output Q(yn) of the time-interleaved (parallel) modulator is described by the difference equation
            Q      ⁡              [                  y          n                ]              =          Q      ⁡              [                              x                          n              -              1                                +                      x                          n              -              2                                -                      Q            ⁡                          (                              y                                  n                  -                  1                                            )                                -                      Q            ⁡                          (                              y                                  n                  -                  2                                            )                                +                      y                          n              -              2                                      ]              ,where the Q(•) operator represents quantization (rounding). The above difference equation results in a STF(z)=z−1 (i.e., an all-pass response) and a NTF(z)=1−z−1, where z−1 represents a full-rate delay, equal to one period of the effective sampling rate fS. Although the STF and NTF of the time-interleaved ΔΣ modulator are equal to those of a full-rate ΔΣ modulator with a first-order shaping (i.e., a ΔΣ modulator which is not time-interleaved), the output of the circuit is a function of a previous output Q(yn−1) which has been delayed by only one full-rate delay (i.e., one period of the effective sampling rate fS) relative to the output Q[yn]. The present inventor has observed that the need to feed back and process outputs that are delayed by only one full-rate period of 1/fS (i.e., the need for processing computations to take place within one full-rate cycle), rather than one sub-rate period of m/fS=2/fS, creates a race condition that forces circuit 80A to operate at speeds equivalent to the full-rate sampling frequency of fS, rather than the intended sub-rate speed of
            1      m        ·          f      S        =            1      2        ·                  f        S            .      This race condition occurs because the difference and quantization functions of the time-interleaved modulator are not implemented as true polyphase (multirate) operations. A similar race condition occurs in the implementation of circuit 80B, which has an output Q(yn) that is described by the difference equation
      Q    ⁡          (              y        n            )        =      Q    ⁡          [                        x                      n            -            2                          +                  2          ·                      x                          n              -              3                                      +                  x                      n            -            4                          -                  Q          ⁡                      (                          y                              n                -                1                                      )                          -                  2          ·                      Q            ⁡                          (                              y                                  n                  -                  2                                            )                                      -                  Q          ⁡                      (                          y                              n                -                3                                      )                          +                  Q          ⁡                      (                          y                              n                -                4                                      )                          +                  2          ·                      y                          n              -              2                                      -                  y                      n            -            4                              ]      (i.e., assuming no implicit quantizer delay). Since the output of circuit 80B also depends on an output Q(yn−1) that has been delayed by only one full-rate period equal to 1/fS, the circuit also must operate at a full-rate of fS, rather than the intended sub-rate of
            1      m        ·          f      S        =            1      2        ·                  f        S            .      In addition to the computational race condition, the present inventor has discovered that circuit 80B exhibits three other undesirable properties: 1) the time-interleaved modulator has a signal transfer function STF(z)=z−2·(1+z−1)2/(1+z−1+z−3) which deviates from a true all-pass response of STF(z)=z−k; 2) the time-interleaved modulator has a noise transfer function NTF(z)=(1−z−1)2/(1+z−1+z−3) which deviates from the desired form of (1−z−1)P for a full-rate lowpass modulator; and 3) the cascaded integrator structure of the second-order modulator is impractical for use in bandpass converter applications because second-order (bandpass) NTFs of the form (1+ρ·z−1+z−2)P, where −2≦ρ≦+2, cannot be factored into cascaded first-order functions of the form (1+α·z−1)·(1+β·z−1).
Besides utilization in analog-to-digital (A/D) converter applications, time-interleaved ΔΣ modulators are employed in conventional circuits which attempt to improve the effective sampling rates and/or instantaneous bandwidths of digital-to-analog (D/A) converters. An example is conventional D/A converter circuit 80C, illustrated in FIG. 5C, which receives a high-rate digital input and consists of: 1) a time-interleaved ΔΣ modulator (e.g., modulator 16A) with an error-feedback structure and a time-interleaving factor of m (i.e., the modulator has m parallel processing paths); and 2) an m-to-1 multiplexer (e.g., multiplexer 16B) with m inputs and one output. See J. Pham and A. C. Carusone, “A Time-Interleaved ΔΣ-DAC Architecture Clocked at the Nyquist Rate,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2008. The parallel outputs of modulator 16A represent subsampled sequences at different sample-time offsets (i.e., phases), such that data samples from the first parallel output correspond to subsampling by m at the first sample-time offset, and data samples from the mth parallel output correspond to subsampling by m at the mth sample-time offset. Output multiplexer 16B converts the m parallel outputs, which switch (toggle) at a sub-rate of 1/m·fS, into a single output which switches (toggles) at the full-rate of fS. The operation of conventional multiplexer 16B can be represented functionally as upsampling (i.e., zero insertion), delaying, and combining. As illustrated, time-interleaved ΔΣ modulator 16A comprises: 1) polyphase loop filter 15 with m inputs and m outputs; 2) an array consisting of m truncation/rounding elements (e.g., quantization circuits 10A&B); and 3) multiple adders and subtractors (e.g., arithmetic operators 8A-D). Conventionally, loop filter 15 is implemented as a parallel circuit with m processing paths, using polyphase decomposition techniques for finite-impulse response (FIR) filters. Each of the m parallel paths is coupled to a quantization circuit (e.g., quantizers 10A&B) and arithmetic operators (e.g., adders 8A&B and subtractors 8C&D), which are simply replicated multiple times rather than being subjected to a polyphase decomposition process.
The present inventor has discovered that like conventional circuits which utilize time-interleaved ΔΣ modulators for A/D conversion, race conditions (i.e., conditions where outputs must be fed back as inputs for processing within one full-rate cycle) limit the effective sampling rate and instantaneous bandwidth of conventional circuits which utilize time-interleaved ΔΣ modulators for D/A conversion. More specifically, race conditions occur because in these conventional D/A converters (e.g., circuit 80C), polyphase decomposition is applied to only a portion of the time-interleaved ΔΣ modulator. As illustrated by conventional converter 80C, shown in FIG. 5C, the loop filter (e.g., loop filter 15) of modulator 16A is a polyphase structure, while truncation elements (e.g., quantizers 10A&B) and arithmetic operators (e.g., subtractors 8C&D) are simply replicated (i.e., duplicated without polyphase decomposition). As a result of polyphase decomposition, the computations associated with loop filter 15 would occur at the subsampling rate of 1/m·fS, if loop filter 15 operated as a standalone filter, rather than as a component in the feedback loop of a larger system (i.e., a ΔΣ modulator). It is well understood by those skilled in the art (i.e., see the filter decomposition discussion in Pham 2008), however, that for a polyphase loop filter having a response of order n (i.e., a discrete-time transfer function where the highest power of delay operator z is n), the computation of each filter output (e.g., the input to adders 8A&B) is a function of n previous inputs, or for the case of a time-interleaved modulator, n previous modulator outputs (i.e., the inputs to loop filter 15 are the outputs of quantizers 10A&B after further processing within subtractors 8C&D). For shaping of quantization noise, loop filter 15 must have a response with nonzero order (i.e., n≧1), and therefore, its operation is such that: 1) the second output of the loop filter cannot be computed until the first input of the loop filter is ready (i.e., until the loop filter input that is coupled to quantizer 10B and subtractor 8D is available); 2) the third output of the loop filter cannot be computed until the second input of the loop filter is ready; and ultimately 3) the mth output of the loop filter (i.e., the loop filter output that is coupled to quantizer 10A and subtractor 8C) cannot be computed until the mth−1 input of the loop filter is ready. As a result of the above sequential processing operation, each of the m modulator outputs is a function of a previous modulator output that has been delayed by only one full-rate cycle of fS (i.e., the delay between the mth−1 modulator output and the m modulator output is only one full-rate sampling period equal to 1/fS). More specifically, although the clocking frequency of each modulator is the sub-rate of
            f      CLK        =                  1        m            ·              f        S              ,computational results must propagate from the first modulator output (i.e., the output of quantizer 10B) to the input of the mth truncation element (i.e., the input of quantizer 10A) in a time of less than m full-rate cycles (i.e., a total time of less than m/fS). Consequently, the modulator computations occur at a speed equivalent to the full-rate sampling frequency of fS, or with a computational latency of 1/fS, to ensure that m computations (i.e., one computation per parallel path) can traverse through the parallel processing blocks during the allotted time of m/fS. The maximum effective sampling rate of conventional converter 80C is further constrained because the conventional m-to-1 multiplexer (e.g., multiplexer 16B), which combines modulator outputs, must run at the full-rate of fS, requiring the multiplexer to be implemented using high-speed circuitry with correspondingly high power consumption.
The present inventor has discovered that conventional lowpass ΔΣ converters, as illustrated in FIGS. 2A-C, and conventional bandpass ΔΣ converters, as illustrated in FIG. 3A, have several disadvantages that limit their utility in discrete-to-linear (digital-to-analog) converter applications requiring very high instantaneous bandwidth and high resolution. The present inventor also has discovered that these disadvantages cannot be overcome by: 1) direct adaptations of the conventional parallel processing approaches devised for A/D conversion, as illustrated in FIG. 4A&B; or 2) by adopting conventional time-interleaved approaches for ΔΣ modulation, as illustrated in FIGS. 5A-C. These disadvantages, which are discussed in greater detail in the Description of the Preferred Embodiment(s) section, include: 1) conversion bandwidth that is limited by the narrow lowpass, or narrow bandpass, filtering operations used to attenuate the shaped quantization noise and errors; 2) conversion resolution (SNDR) that is limited by the clock frequency fCLK of the delta-sigma modulator (i.e., the clock frequency of a two-level quantizer); 3) conversion resolution that is limited by a low-order noise-shaped response (i.e., generally second-order for bandpass modulators), which is needed for stable operation with two-level quantizers; and 4) effective sampling rates that are limited by race conditions occurring when outputs must be fed back as inputs for processing within one full-rate cycle. In addition, conventional oversampling digital-to-analog converters cannot be operated in parallel as hybrid filter banks (i.e., HFB scheme) or multi-band arrays (i.e., MBΔΣ scheme), without suffering from the amplitude and group delay distortion introduced by imperfect analog filter banks, and/or the nonlinear (intermodulation) distortion introduced by upconverting analog mixers. Because of these disadvantages, the resolution of conventional oversampling converters cannot be increased without: 1) reducing bandwidth to improve the quantization noise attenuation of the output (smoothing) filters; or 2) increasing the converter sampling rate by using digital circuits with higher switching speeds (i.e., or sampling rates), since high-order modulators are unstable with two-level quantization. In addition, conventional oversampling converters employ delta-sigma modulator structures that do not provide a means of dynamically varying, or re-programming, the frequency (fnotch) where a minimum magnitude occurs in the quantization-noise response. The present inventor has discovered that such a feature can be advantageous in multi-mode applications (e.g., frequency synthesizers and tunable radios) where, depending on its programming, a single converter preferably can operate on different (multiple) frequency bands.